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? 2008-2013 microchip technology inc. ds20002122b-page 1 11aa02e48/11aa02e64 device selection table features: pre-programmed globally unique, 48-bit or 64-bit node address compatible with eui-48? and eui-64? single i/o, uni/o ? serial interface bus low-power cmos technology - 1 ma active current, typical - 1 a standby current (max.) 256 x 8 bit organization schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 kbps max. bit rate C equivalent to 100 khz clock frequency self-timed write cycle (including auto-erase) page-write buffer for up to 16 bytes status register for added control: - write enable latch bit - write-in-progress bit block write protection - protect none, 1/4, 1/2 or all of array built-in write protection - power-on/off data protection circuitry - write enable latch high reliability - endurance: 1,000,000 erase/write cycles - data retention: > 200 years - esd protection: > 4,000v 3-lead sot-23 and 8-lead soic packages pb-free and rohs compliant available temperature ranges: description: the microchip technology inc. 11aa02e48/ 11aa02e64 (11aa02exx*) device is a 2 kbit serial electrically erasable prom. the device is organized in blocks of x8-bit memory and support the patented** single i/o uni/o ? serial bus. by using manchester encoding techniques, the clock and data are combined into a single, serial bit stream (scio), where the clock signal is extracted by the receiver to correctly decode the timing and value of each bit. low-voltage design permits operation down to 1.8v, with standby and active currents of only 1 ua and 1 ma, respectively. the 11aa02exx is available in standard 8-lead soic and 3-lead sot-23 packages. package types (not to scale) pin function table part number density (bits) v cc range page size (bytes) temp. ranges packages node address 11aa02e48 2k 1.8-5.5v 16 i sn, tt eui-48 ? 11aa02e64 2k 1.8-5.5v 16 i sn, tt eui-64 ? - industrial (i): -40c to +85c name function scio serial clock, data input/output v ss ground v cc supply voltage ncnc nc v ss 12 3 4 87 6 5 v cc ncnc scio soic (sn) sot23 2 3 1 scio v cc v ss (tt) 2k uni/o ? serial eeproms with eui-48? or eui-64? node identity * 11aa02exx is used in this document as a generic part number for the 11aa02e48 and 11aa02e64 devices. ** microchips uni/o ? bus products are covered by the following pate nts issued in the u.s.a.: 7,376,020 and 7,788,430. downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 2 ? 2008-2013 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v scio w.r.t. v ss ............................................................................................................................... ..... -0.6v to v cc +1.0v storage temperature ............................................................................................................ .....................-65c to 150c ambient temperature under bias ................................................................................................. ................-40c to 85c esd protection on all pins ..................................................................................................... .....................................4 kv table 1-1: dc characteristics ? notice : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditio ns for an extended period of time may affect device reliability. dc characteristics electrical characteristics: industrial (i): v cc = 2.5v to 5.5v t a = -40c to +85c v cc = 1.8v to 2.5v t a = -20c to +85c param. no. sym. characteristic min. max. units test conditions d1 v ih high-level input voltage 0.7*v cc v cc +1 v d2 v il low-level input voltage -0.3 -0.3 0.3*v cc 0.2*v cc vv v cc ??? 2.5v v cc < 2.5v d3 v hys hysteresis of schmitt trigger inputs (scio) 0.05*vcc v v cc ??? 2.5v ( note 1 ) d4 v oh high-level output voltage v cc -0.5 v cc -0.5 vv i oh = -300 ? a, v cc = 5.5v i oh = -200 ? a, vcc = 2.5v d5 v ol low-level output voltage 0.4 0.4 vv i o i = 300 ? a, v cc = 5.5v i o i = 200 ? a, vcc = 2.5v d6 i o output current limit ( note 2 ) 43 mama v cc = 5.5v ( note 1 ) vcc = 2.5v ( note 1 ) d7 i li input leakage current (scio) 1 ? av in = v ss or v cc d8 c int internal capacitance (all inputs and outputs) 7p f t a = 25c, f clk = 1 mhz, v cc = 5.0v ( note 1 ) d9 i cc read read operating current 31 mama v cc =5.5v, f bus =100 khz, c b =100 pf v cc =2.5v, f bus =100 khz, c b =100 pf d10 i cc write write operating current 53 mama v cc = 5.5v v cc = 2.5v d11 iccs standby current 1 ? av cc = 5.5v, t a = 85c d12 i cci idle mode current 50 ? av cc = 5.5v note 1: this parameter is periodically sampled and not 100% tested. 2: the scio output driver impedance will vary to ensure i o is not exceeded. downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 3 11aa02e48/11aa02e64 table 1-3: ac test conditions table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = 2.5v to 5.5v t a = -40c to +85c v cc = 1.8v to 2.5v t a = -20c to +85c param. no. sym. characteristic min. max. units test conditions 1f bus serial bus frequency 10 100 khz 2t e bit period 10 100 s 3t ijit input edge jitter tol e r an ce 0 . 0 6u i ( note 3 ) 4f drift serial bus frequency drift rate tolerance 0.50 % per byte 5f dev serial bus frequency drift limit 5% p e r command 6t ojit output edge jitter 0.25 ui ( note 3 ) 7t r scio input rise time ( note 1 ) 100 ns 8t f scio input fall time ( note 1 ) 100 ns 9t stby standby pulse time 600 s 10 t ss start header setup time 10 s 11 t hdr start header low pulse time 5 s 12 t sp input filter spike suppression (scio) 5 0n s ( note 1 ) 13 t wc write cycle time (byte or page) 5 10 msms write, wrsr commands eral, setal commands 14 endurance (per page) 1m cycles 25c, v cc = 5.5v ( note 2 ) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endu rance estimates in a specific application, please consult the total endurance ? model which can be obtained on microchips web site: www.microchip.com. 3: a unit interval (ui) is equal to 1-bit period (t e ) at the current bus frequency. ac waveform: v lo = 0.2v v hi = v cc - 0.2v c l = 100 pf timing measurement reference level input 0.5 v cc output 0.5 v cc downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 4 ? 2008-2013 microchip technology inc. figure 1-1: bus timing C start header figure 1-2: bus timing C data figure 1-3: bus timing C standby pulse figure 1-4: bus timing C jitter scio 2 data 0 data 1 data 0 data 1 data 0 data 1 data 0 data 1 mak bit nosak bit 11 10 2 scio 7 8 data 0 data 1 data 1 data 0 12 scio 9 standby mode ideal edge 3 2 3 6 6 2 6 6 ideal edge ideal edge ideal edge from master from master from slave from slave downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 5 11aa02e48/11aa02e64 2.0 functional description 2.1 principles of operation the 11aa02exx family of serial eeproms support the uni/o ? protocol. they can be interfaced with microcontrollers, including microchips pic ? microcon- trollers, asics, or any other device with an available discrete i/o line that can be configured properly to match the uni/o protocol. the 11aa02exx devices contain an 8-bit instruction register. the devices are accessed via the scio pin. data is embedded into the i/o stream through manchester encoding. the bus is controlled by a master device which determines the clock period, con- trols the bus access and initiates all operations, while the 11aa02exx works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is active. figure 2-1: block diagram scio status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic v cc v ss current- limited slope control downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 6 ? 2008-2013 microchip technology inc. 3.0 bus characteristics 3.1 standby pulse when the master has control of scio, a standby pulse can be generated by holding scio high for t stby . at this time, the 11aa02exx will reset and return to standby mode. subsequently, a high-to-low transition on scio (the first low pulse of the header) will return the device to the active state. once a command is terminated satisfactorily (i.e., via a nomak/sak combination during the acknowledge sequence), performing a standby pulse is not required to begin a new command as long as the device to be selected is the same device selected during the previ- ous command. however, a period of t ss must be observed after the end of the command and before the beginning of the start header. after t ss , the start header (including t hdr low pulse) can be transmitted in order to begin the new command. if a command is terminated in any manner other than a nomak/sak combination, then the master must perform a standby pulse before beginning a new command, regardless of which device is to be selected. an example of two consecutive commands is shown in figure 3-1 . note that the device address is the same for both commands, indicating that the same device is being selected both times. a standby pulse cannot be generated while the slave has control of scio. in this situation, the master must wait for the slave to finish transmitting and to release scio before the pulse can be generated. if, at any point during a command an error is detected by the master, a standby pulse should be generated and the command should be performed again. figure 3-1: consecut ive commands example 3.2 start data transfer all operations must be preceded by a start header. the start header consists of holding scio low for a period of t hdr , followed by transmitting an 8-bit 01010101 code. this code is used to synchronize the slaves internal clock period with the masters clock period, so accurate timing is very important. when a standby pulse is not required (i.e., between successive commands to the same device), a period of t ss must be observed after the end of the command and before the beginning of the start header. figure 3-2 shows the waveform for the start header, including the required acknowledge sequence at the end of the byte. figure 3-2: start header note: after a por/bor event occurs, a low-to- high transition on scio must be gener- ated before proceeding with communica- tion, including a standby pulse. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak nosak sak standby pulse (1) 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak nosak sak nomak sak t ss note 1: after a por/bor event, a low-to-high transition on scio is required to occur before the first standby pulse. scio data 0 data 1 data 0 data 1 data 0 data 1 data 0 data 1 mak nosak t ss t hdr downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 7 11aa02e48/11aa02e64 3.3 acknowledge an acknowledge routine occurs after each byte is transmitted, including the start header. this routine consists of two bits. the first bit is transmitted by the master, and the second bit is transmitted by the slave. the master acknowledge, or mak, is signified by trans- mitting a 1 , and informs the slave that the current operation is to be continued. conversely, a not acknowledge, or nomak, is signified by transmitting a 0 , and is used to end the current operation (and initiate the write cycle for write operations). the slave acknowledge, or sak, is also signified by transmitting a 1 , and confirms proper communication. however, unlike the nomak, the nosak is signified by the lack of a middle edge during the bit period. a nosak will occur for the following events: following the start header following the device address, if no slave on the bus matches the transmitted address following the command byte, if the command is invalid, including read, crrd, write, wrsr, setal, and eral during a write cycle. if the slave becomes out of sync with the master if a command is terminated prematurely by using a nomak, with the exception of immediately after the device address. see figure 3.3 and figure 3-4 for details. if a nosak is received from the slave after any byte (except the start header), an error has occurred. the master should then perform a standby pulse and begin the desired command again. figure 3-3: acknowledge routine figure 3-4: acknowledge bits 3.4 device addressing a device address byte is the first byte received from the master device following the start header. the device address byte consists of a four-bit family code, for the 11aa02exx this is set as 1010 . the last four bits of the device address byte are the device code, which is hardwired to 0000 . figure 3-5: device address byte allocation 3.5 bus conflict protection to help guard against high current conditions arising from bus conflicts, the 11aa02exx features a current- limited output driver. the i ol and i oh specifications describe the maximum current that can be sunk or sourced, respectively, by the scio pin. the 11aa02exx will vary the output driver impedance to ensure that the maximum current level is not exceeded. note: a mak must always be transmitted following the start header. note: when a nomak is used to end a write or wrsr instruction, the write cycle is not initiated if no bytes of data have been received. note: in order to guard against bus contention, a nosak will occur after the start header. master slave mak sak mak ( 1 ) nomak ( 0 ) sak ( 1 ) nosak (1) note 1: valid sak. a nosak is defined as any sequence that is not a 1010 000 mak slave address 0 sak downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 8 ? 2008-2013 microchip technology inc. 3.6 device standby the 11aa02exx features a low-power standby mode during which the device is waiting to begin a new com- mand. a high-to-low transition on scio will exit low- power mode and prepare the device for receiving the start header. standby mode will be entered upon the following conditions: a nomak followed by a sak (i.e., valid termina- tion of a command) reception of a standby pulse 3.7 device idle the 11aa02exx features an idle mode during which all serial data is ignored until a standby pulse occurs. idle mode will be entered upon the following condi- tions: invalid device address invalid command byte, including read, crrd, write, wrsr, setal and eral during a write cycle. missed edge transition reception of a mak following a wren, wrdi, setal, or eral command byte reception of a mak following the data byte of a wrsr command an invalid start header will indirectly cause the device to enter idle mode. whether or not the start header is invalid cannot be detected by the slave, but will prevent the slave from synchronizing properly with the master. if the slave is not synchronized with the master, an edge transition will be missed, thus causing the device to enter idle mode. 3.8 synchronization at the beginning of every command, the 11aa02exx utilizes the start header to determine the masters bus clock period. this period is then used as a reference for all subsequent communication within that command. the 11aa02exx features re-synchronization circuitry which will monitor the position of the middle data edge during each mak bit and subsequently adjust the inter- nal time reference in order to remain synchronized with the master. there are two variables which can cause the 11aa02exx to lose synchronization. the first is frequency drift, defined as a change in the bit period, t e . the second is edge jitter, which is a single occur- rence change in the position of an edge within a bit period, while the bit period itself remains constant. 3.8.1 frequency drift within a system, there is a possibility that frequencies can drift due to changes in voltage, temperature, etc. the re-synchronization circuitry provides some toler- ance for such frequency drift. the tolerance range is specified by two parameters, f drift and f dev . f drift specifies the maximum tolerable change in bus fre- quency per byte. f dev specifies the overall limit in fre- quency deviation within an operation (i.e., from the end of the start header until communication is terminated for that operation). the start header at the beginning of the next operation will reset the re-synchronization circuitry and allow for another f dev amount of frequency drift. 3.8.2 edge jitter ensuring that edge transitions from the master always occur exactly in the middle or end of the bit period is not always possible. therefore, the re-synchronization circuitry is designed to provide some tolerance for edge jitter. the 11aa02exx adjusts its phase every mak bit, so t ijit specifies the maximum allowable peak-to-peak jitter relative to the previous mak bit. since the position of the previous mak bit would be difficult to measure by the master, the minimum and maximum jitter values for a system should be considered the worst-case. these values will be based on the execution time for different branch paths in software, jitter due to thermal noise, etc. the difference between the minimum and maximum values, as a percentage of the bit period, should be cal- culated and then compared against t ijit to determine jitter compliance. note: in the case of the write, wrsr, setal, or eral commands, the write cycle is initiated upon receipt of the nomak, assuming all other write requirements have been met. note: because the 11aa02exx only re-syn- chronizes during the mak bit, the overall ability to remain synchronized depends on a combination of frequency drift and edge jitter (i.e., if the mak bit edge is experienc- ing the maximum allowable edge jitter, then there is no room for frequency drift). conversely, if the frequency has drifted to the maximum amount tolerable within a byte, then no edge jitter can be present. downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 9 11aa02e48/11aa02e64 4.0 device commands after the device address byte, a command byte must be sent by the master to indicate the type of operation to be performed. the code for each instruction is listed in table 4-1 . table 4-1: instruction set 4.1 read instruction the read command allows the master to access any memory location in a random manner. after the read instruction has been sent to the slave, the two bytes of the word address are transmitted, with an acknowl- edge sequence being performed after each byte. then, the slave sends the first data byte to the master. if more data is to be read, the master sends a mak, indicating that the slave should output the next data byte. this continues until the master sends a nomak, which ends the operation. to provide sequential reads in this manner, the 11aa02exx contains an internal address pointer which is incremented by one after the transmission of each byte. this address pointer allows the entire mem- ory contents to be serially read during one operation. when the highest address is reached, the address pointer rolls over to address 0x00 if the master chooses to continue the operation by providing a mak. figure 4-1: read command sequence instruction name instruction code hex code description read 0000 0011 0x03 read data from memory array beginning at specified address crrd 0000 0110 0x06 read data from current location in memory array write 0110 1100 0x6c write data to memory array beginning at specified address wren 1001 0110 0x96 set the write enable latch (enable write operations) wrdi 1001 0001 0x91 reset the write enable latch (disable write operations) rdsr 0000 0101 0x05 read status register wrsr 0110 1110 0x6e write status register eral 0110 1101 0x6d write 0x00 to entire array setal 0110 0111 0x67 write 0xff to entire array 765 4 data byte 1 321 0 765 4 data byte 2 321 0 765 4 data byte n 321 0 scio mak mak nomak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 01 0 0 0 0 01 mak nosak sak standby pulse scio sak 15 14 13 12 word address msb 11 10 9 8 mak sak 765 4 word address lsb 321 0 mak sak sak sak sak downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 10 ? 2008-2013 microchip technology inc. 4.2 current address read ( crrd) instruction the internal address counter featured on the 11aa02exx maintains the address of the last memory array location accessed. the crrd instruction allows the master to read data back beginning from this current location. consequently, no word address is provided upon issuing this command. note that, except for the initial word address, the read and crrd instructions are identical, including the ability to continue requesting data through the use of maks in order to sequentially read from the array. as with the read instruction, the crrd instruction is terminated by transmitting a nomak. table 4-2 lists the events upon which the internal address counter is modified. table 4-2: internal address counter figure 4-2: crrd command sequence command event action power-on reset counter is undefined read or write mak edge following each address byte counter is updated with newly received value read , write , or crrd mak/nomak edge following each data byte counter is incre- mented by 1 note: if, following each data byte in a read , write , or crrd instruction, neither a mak nor a nomak edge is received (i.e., if a standby pulse occurs instead), the internal address counter will not be incre- mented. note: during a write command, once the last data byte for a page has been loaded, the internal address pointer will rollover to the beginning of the selected page. 765 4 data byte 1 321 0 765 4 data byte 2 321 0 765 4 data byte n 321 0 scio mak mak nomak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 0 0 0 0 01 mak nosak sak standby pulse scio sak sak sak sak downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 11 11aa02e48/11aa02e64 4.3 write instruction prior to any attempt to write data to the 11aa02exx, the write enable latch must be set by issuing the wren instruction (see section 4.4 write enable (wren) and write disable (wrdi) instructions ). once the write enable latch is set, the user may proceed with issuing a write instruction (including the header and device address bytes) followed by the msb and lsb of the word address. once the last acknowledge sequence has been performed, the master transmits the data byte to be written. the 11aa02exx features a 16-byte page buffer, mean- ing that up to 16 bytes can be written at one time. to utilize this feature, the master can transmit up to 16 data bytes to the 11aa02exx, which are temporarily stored in the page buffer. after each data byte, the master sends a mak, indicating whether or not another data byte is to follow. a nomak indicates that no more data is to follow, and as such will initiate the internal write cycle. upon receipt of each word, the four lower-order address pointer bits are internally incremented by one. the higher-order bits of the word address remain con- stant. if the master should transmit data past the end of the page, the address counter will roll over to the begin- ning of the page, where further received data will be written. figure 4-3: write command sequence note: if a nomak is generated before any data has been provided, or if a standby pulse occurs before the nomak is generated, the 11aa02exx will be reset, and the write cycle will not be initiated. note: page write operations are limited to writ- ing bytes within a single physical page, regardless of the number of bytes actu- ally being written. physical page boundar- ies start at addresses that are integer multiples of the page size (16 bytes) and end at addresses that are integer multi- ples of the page size minus 1. as an example, the page that begins at address 0x30 ends at address 0x3f. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previ- ously stored there), instead of being writ- ten to the next page as might be expected. it is therefore necessary for the applica- tion software to prevent page write opera- tions that would attempt to cross a page boundary. 765 4 data byte 1 321 0 765 4 data byte 2 321 0 765 4 data byte n 321 0 scio mak mak no mak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 1 0 1 1 00 mak nosak sak standby pulse scio sak 15 14 13 12 word address msb 11 10 9 8 mak sak 765 4 word address lsb 321 0 mak sak sak sak sak twc downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 12 ? 2008-2013 microchip technology inc. 4.4 write enable ( wren ) and write disable ( wrdi ) instructions the 11aa02exx contains a write enable latch. see table 6-1 for the write-protect functionality matrix. this latch must be set before any write operation will be completed internally. the wren instruction will set the latch, and the wrdi instruction will reset the latch. the following is a list of conditions under which the write enable latch will be reset: power-up wrdi instruction successfully executed wrsr instruction successfully executed write instruction successfully executed eral instruction successfully executed setal instruction successfully executed figure 4-4: write enable command sequence figure 4-5: write disable command sequence note: the wren and wrdi instructions must be terminated with a nomak following the command byte. if a nomak is not received at this point, the command will be considered invalid, and the device will go into idle mode without responding with a sak or executing the command. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 0 1 0 0 11 nomak nosak sak standby pulse scio sak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 01 0 1 0 0 10 nomak nosak sak standby pulse scio sak downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 13 11aa02e48/11aa02e64 4.5 read status register ( rdsr ) instruction the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: the write-in-process (wip) bit indicates whether the 11aa02exx is busy with a write operation. when set to a 1 , a write is in progress, when set to a 0 , no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the status of the write enable latch. when set to a 1 , the latch allows writes to the array, when set to a 0 , the latch prohibits writes to the array. this bit is set and cleared using the wren and wrdi instructions, respectively. this bit is read-only for any other instruction. the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user through the wrsr instruction. these bits are nonvolatile. the wip and wel bits will update dynamically (asyn- chronous to issuing the rdsr instruction). further- more, after the status register data is received, the master can provide a mak during the acknowledge sequence to request that the data be transmitted again. this allows the master to continuously monitor the wip and wel bits without the need to issue another full command. once the master is finished, it provides a nomak to end the operation. figure 4-6: read status register command sequence 7654 3 2 1 0 xxxx bp1 bp0 wel wip note: bits 4-7 are dont cares, and will read as 0 . note: if read status register command is initiated while the 11aa02exx is currently executing an internal write cycle on the status register, the new block protection bit values will be read during the entire command. note: the current drawn for a read status register command during a write cycle is a combination of the i cc read and i cc write operating currents. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 11 0 0 0 0 00 mak nosak sak standby pulse scio sak status register data 321 0 nomak sak the status register data can continuously be read, or polled, by transmitting a mak in place of the nomak. note: 0 0 0 0 downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 14 ? 2008-2013 microchip technology inc. 4.6 write status register ( wrsr ) instruction the wrsr instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write-protect none, one, two, or all four of the seg- ments of the array. the partitioning is controlled as illustrated in tab l e 4 - 3 . after transmitting the status register data, the master must transmit a nomak during the acknowledge sequence in order to initiate the internal write cycle. table 4-3: array protection figure 4-7: write status register command sequence note: the wrsr instruction must be terminated with a nomak following the data byte. if a nomak is not received at this point, the command will be considered invalid, and the device will go into idle mode without responding with a sak or executing the command. bp1 bp0 array addresses write-protected 00 none 01 upper 1/4 (c0h-ffh) 10 upper 1/2 (80h-ffh) 11 all (00h-ffh) 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 1 0 1 1 01 mak nosak sak standby pulse scio sak 765 4 status register data 321 0 nomak sak twc downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 15 11aa02e48/11aa02e64 4.7 erase all ( eral ) instruction the eral instruction allows the user to write 0x00 to the entire memory array with one command. note that the write enable latch (wel) must first be set by issuing the wren instruction. once the write enable latch is set, the user may pro- ceed with issuing a eral instruction (including the header and device address bytes). immediately after the nomak bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to 0x00. the eral instruction is ignored if either of the block protect bits (bp0, bp1) are not 0, meaning 1/4, 1/2, or all of the array is protected. figure 4-8: erase all command sequence 4.8 set all ( setal ) instruction the setal instruction allows the user to write 0xff to the entire memory array with one command. note that the write enable latch (wel) must first be set by issuing the wren instruction. once the write enable latch is set, the user may pro- ceed with issuing a setal instruction (including the header and device address bytes). immediately after the nomak bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to 0xff . the setal instruction is ignored if either of the block protect bits (bp0, bp1) are not 0 , meaning 1/4, 1/2, or all of the array is protected. figure 4-9: set all command sequence note: the eral instruction must be terminated with a nomak following the command byte. if a nomak is not received at this point, the command will be considered invalid, and the device will go into idle mode without responding with a sak or executing the command. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 11 1 0 1 1 00 nomak nosak sak standby pulse scio sak twc note: the setal instruction must be termi- nated with a nomak following the com- mand byte. if a nomak is not received at this point, the command will be consid- ered invalid, and the device will go into idle mode without responding with a sak or executing the command. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 11 0 0 1 1 01 nomak nosak sak standby pulse scio sak twc downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 16 ? 2008-2013 microchip technology inc. 5.0 data protection the following protection has been implemented to prevent inadvertent writes to the array: the write enable latch (wel) is reset on power- up a write enable ( wren ) instruction must be issued to set the write enable latch after a write, eral, setal, or wrsr command, the write enable latch is reset commands to access the array or write to the status register are ignored during an internal write cycle and programming is not affected 6.0 power-on state the 11aa02exx powers on in the following state: the device is in low-power shutdown mode, requiring a low-to-high transition on scio to enter idle mode the write enable latch (wel) is reset the internal address pointer is undefined a low-to-high transition, standby pulse and subse- quent high-to-low transition on scio (the first low pulse of the header) are required to enter the active state . table 6-1: write protec t functionality matrix wel protected blocks unprotected blocks status register 0 protected protected protected 1 protected writable writable downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 17 11aa02e48/11aa02e64 7.0 pre-programmed eui-48? or eui-64? node address the 11aa02exx is programmed at the factory with a globally unique node address stored in the upper 1/4 of the array and write-protected through the status register. the remaining 1,536 bits are available for application use. figure 7-1: memory organization 7.1 factory-programmed write protection in order to help guard against accidental corruption of the node address, the bp1 and bp0 bits of the status register are programmed at the factory to 0 and 1 , respectively, as shown in the following table: this protects the upper 1/4 of the array (0xc0 to 0xff) from write operations. this array block can be utilized for writing by clearing the bp bits with a write status register ( wrsr ) instruction. note that if this is per- formed, care must be taken to prevent overwriting the node address value. 7.2 eui-48 ? node address (11aa02e48) the 6-byte eui-48? node address value of the 11aa02e48 is stored in array locations 0xfa through 0xff, as shown in figure 7-2 . the first three bytes are the organizationally unique identifier (oui) assigned to microchip by the ieee registration authority. cur- rently, microchips ouis are 0x0004a3 and 0x001ec0, though this will change as addresses are exhausted. the remaining three bytes are the extension identifier, and are generated by microchip to ensure a globally- unique, 48-bit value. 7.2.1 eui-64? support using the 11aa02e48 the pre-programmed eui-48 node address of the 11aa02e48 can easily be encapsulated at the applica- tion level to form a globally unique, 64-bit node address for systems utilizing the eui-64 standard. this is done by adding 0xfffe between the oui and the extension identifier, as shown below. figure 7-2: eui-48 node address physic al memory map example (11aa02e48) 7654 3 2 1 0 xxxx bp1 bp0 wel wip 01 00h c0h ffh write-protected node address block standard eeprom note: as an alternative, the 11aa02e64 features an eui-64 node address that can be used in eui-64 applications directly without the need for encapsulation, thereby simplifying system software. see section 7.3 eui-64? node address (11aa02e64) for details. fah ffh 24-bit organizationally unique identifier 24-bit extension identifier 00h 04h a3h 12h 34h 56h corresponding eui-48? node address: 00-04-a3-12-34-56 description data array address corresponding eui-64? node address after encapsulation: 00-04-a3-ff-fe-12-34-56 downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 18 ? 2008-2013 microchip technology inc. 7.3 eui-64 ? node address (11aa02e64) the 8-byte eui-64? node address value of the 11aa02e64 is stored in array locations 0xf8 through 0xff, as shown in figure 7-3 . the first three bytes are the organizationally unique identifier (oui) assigned to microchip by the ieee registration authority. cur- rently, microchips ouis are 0x0004a3 and 0x001ec0, though this will change as addresses are exhausted. the remaining five bytes are the extension identifier, and are generated by microchip to ensure a globally- unique, 64-bit value. figure 7-3: eui-64 node address physic al memory map example (11aa02e64) note: in conformance with ieee guidelines, microchip will not use the values 0xfffe and 0xffff for the first two bytes of the eui-64 extension identifier. these two values are specifically reserved to allow applications to encapsulate eui-48 addresses into eui-64 addresses. f8h ffh 24-bit organizationally unique identifier 40-bit extension identifier 00h 04h a3h 12h 34h 56h corresponding eui-64? node address: 00-04-a3-12-34-56-78-90 description data array address 78h 90h downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 19 11aa02e48/11aa02e64 8.0 pin descriptions the descriptions of the pins are listed in tab l e 8 - 1 . table 8-1: pin function table 8.1 serial clock, data input/output (scio) scio is a bidirectional pin used to transfer commands and addresses into, as well as data into and out of, the device. the serial clock is embedded into the data stream through manchester encoding. each bit is represented by a signal transition at the middle of the bit period. name 3-pin sot-23 8-pin soic description scio 1 5 serial clock, data input/output v cc 2 8 supply voltage v ss 3 4 ground nc 1,2,3,6,7 no internal connection downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 20 ? 2008-2013 microchip technology inc. 9.0 packaging information 9.1 package marking information part number 1st line marking code sot-23 soic i temp. i temp. 11aa02e48 e2nn 11a2e48t 11aa02e64 aaannn 11a2e64t 8-lead soic xxxxyyww xxxxxxxt nnn example: sn 1328 11a2e48i 1l7 3 e 3-lead sot-23 (11aa02e48) xxnn example: e217 3-lead sot-23 (11aa02e64) xxxnnn example: aaa1l7 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 21 11aa02e48/11aa02e64 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 22 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 23 11aa02e48/11aa02e64 downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 24 ? 2008-2013 microchip technology inc. b n e e1 2 1 e e1 d a a1 a2 c l downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 25 11aa02e48/11aa02e64 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 26 ? 2008-2013 microchip technology inc. appendix a: revision history revision a (12/2008) original release of this document. revision b (04/2013) revised ac char. max. parameters 3 and 4; added 11aa02e64 part. downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 27 11aa02e48/11aa02e64 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 28 ? 2008-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microc hip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our document ation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds20002122b 11aa02e48/11aa02e64 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 29 11aa02e48/11aa02e64 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x x /x x package temperature tape & reel device device: 11aa02e48 = 2 kbit, 1.8v uni/o serial eeprom with eui-48? node identity 11aa02e64 = 2 kbit, 1.8v uni/o serial eeprom with eui-64? node identity tape & reel: t = tape and reel blank = tube temperature range: i=- 4 0 ? c to+85 ? c(industrial) package: sn = 8-lead plastic soic (3.90 mm body) tt = 3-lead sot 23 (tape and reel only) examples: a) 11aa02e48t-i/tt = 2 kbit, 1.8v serial eeprom with eui-48 node identity, industrial temp., tape & reel, sot-23 package b) 11aa02e48-i/sn = 2 kbit, 1.8v serial eeprom with eui-48 node identity, industrial temp., soic package c) 11aa02e48t-i/sn = 2 kbit, 1.8v serial eeprom with eui-48 node identity, industrial temp., tape & reel, soic package d) 11aa02e64t-i/tt = 2 kbit, 1.8v serial eeprom with eui-64 node identity, industrial temp., tape & reel, sot-23 package e) 11aa02e64-i/sn = 2 kbit, 1.8v serial eeprom with eui-64 node identity, industrial temp., soic package f) 11aa02e64t-i/sn = 2 kbit, 1.8v serial eeprom with eui-64 node identity, industrial temp., tape & reel, soic package range downloaded from: http:///
11aa02e48/11aa02e64 ds20002122b-page 30 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds20002122b-page 31 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2008-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620771570 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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